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Altera_Forum
Honored Contributor
17 years agoi have another problem like this
Error (10397): VHDL Event Expression error at timer.vhd(15): can't form clock edge from S'EVENT by combining it with an expression that depends on a signal besides S Error (10658): VHDL Operator error at timer.vhd(15): failed to evaluate call to operator ""and"" Error: Can't elaborate top-level user hierarchy one more thing i wanna ask you, the package should be written in the coding or separated?