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Honored Contributorchess clock coding using quartus II
i'm a newbie..can u plz guide me to write a code on normal digital chess clock?
14 Replies
Altera_Forumactually its not a homework...its one of my project...
thank you avatar...- Altera_Forum
Too all,
I may be completely wrong here, and Cempaka, please correct me if I am, but..... This sure looks like Cempaka has been assigned a homework problem in a class somewhere and none of us are doing this person any good if we do all the work for him (her). There are a lot of very basic items that can most likely be addressed if you look at the Altera WEB page, Training and take some of the free WEB training classes. http://www.altera.com/education/training/curriculum/fpga/trn-fpga.html I would start at the top on the right, and work my way down. Please let me know if I am wrong or missing the mark. Avatar - Altera_Forum
do u finished the chess clock code? do u mind to post it??
- Altera_Forum
i have another problem like this
Error (10397): VHDL Event Expression error at timer.vhd(15): can't form clock edge from S'EVENT by combining it with an expression that depends on a signal besides S Error (10658): VHDL Operator error at timer.vhd(15): failed to evaluate call to operator ""and"" Error: Can't elaborate top-level user hierarchy one more thing i wanna ask you, the package should be written in the coding or separated? - Altera_Forum
I have copied the code in Quartus II and I am unable to reproduce those messages after a file analyze command. Try to review all your code and search for missing brackets or semicolons. Sorry but I haven't got any other suggestions since I am not able to reproduce the messages.
- Altera_Forum
i have a problem with that coding OD..before i start with my editing the code, i try to run the program..but it keeps telling me there were an error at the area of the last 2 blocks..
Error (10500): VHDL syntax error at cheroy.vhd(165) near text "END"; expecting ";", or an identifier ("end" is a reserved keyword) Error (10500): VHDL syntax error at cheroy.vhd(167) near text "BLOCK"; expecting "(", or an identifier ("block" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at cheroy.vhd(175) near text "END"; expecting ";", or an identifier ("end" is a reserved keyword) can u please help me.. - Altera_Forum
oh dear..you really helped me...thank you soooo much OD...
- Altera_Forum
I have found it for you.
Just go to http://www.gexin.com.cn/uploadfile/document2007620132345.pdf, download the document and go to page 45. Good luck with your design. ;) OD - Altera_Forum
argh...i dont think i can make it in these day..
somebody plz help meee with the state diagram....!!! arggghh... - Altera_Forum
You may have a look at the book "Circuit Design with VHDL" by Volnei A. Pedroni. You can freely download it from www.scribd.com. Chapter 8 is the one dealing with finite state machines. Is it always good for a digital design engineer to have some theoretical overview about FSM design, it is the first step towards a good result.
Good luck. OD
