Altera_Forum
Honored Contributor
Honored Contributorchess clock coding using quartus II
i'm a newbie..can u plz guide me to write a code on normal digital chess clock?
Forum Discussion
14 Replies
Altera_ForumThe chess clock is a simple finite state machine (FSM) which you can firstly design as a state diagram just figuring out the various states in which the machine will work in dependance of the external inputs and of the current states.
After having completed the FSM schematization you will have to translate everything into HDL code (maybe Verilog or VHDL) and put it into a new Quartus II project. Do you need specific help for the chess clock project or also a comprehensive tutorial on Quartus II environment and FSM design?- Altera_Forum
thanks for helping...
i think i need more..because i'm totally blur...i dont know where to start, the state diagram, state table...very blur.... - Altera_Forum
OK, so you need first of all a good book of Digital Electronics Design just to understand how a design idea can be translated into a FSM (which can be described conveniently by a state diagram). After that you will need to have a tutorial of Quartus II environment (directly available after installing Quartus II) and then you need to learn HDL programming.
So you can understand that the process is a bit long and not simply solvable through some forum clues. If you need, I can suggest you some good books for Digital Electronics and for VHDL/Verilog programming Cheers OD - Altera_Forum
i have a book on digital fundamentals n digital logic already...but what i can do only a simple projects, such as vending machine, 7segment.
but when it comes to this, i do not know how to do the state diagram... pls help me.. - Altera_Forum
You may have a look at the book "Circuit Design with VHDL" by Volnei A. Pedroni. You can freely download it from www.scribd.com. Chapter 8 is the one dealing with finite state machines. Is it always good for a digital design engineer to have some theoretical overview about FSM design, it is the first step towards a good result.
Good luck. OD - Altera_Forum
argh...i dont think i can make it in these day..
somebody plz help meee with the state diagram....!!! arggghh... - Altera_Forum
I have found it for you.
Just go to http://www.gexin.com.cn/uploadfile/document2007620132345.pdf, download the document and go to page 45. Good luck with your design. ;) OD - Altera_Forum
oh dear..you really helped me...thank you soooo much OD...
- Altera_Forum
i have a problem with that coding OD..before i start with my editing the code, i try to run the program..but it keeps telling me there were an error at the area of the last 2 blocks..
Error (10500): VHDL syntax error at cheroy.vhd(165) near text "END"; expecting ";", or an identifier ("end" is a reserved keyword) Error (10500): VHDL syntax error at cheroy.vhd(167) near text "BLOCK"; expecting "(", or an identifier ("block" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at cheroy.vhd(175) near text "END"; expecting ";", or an identifier ("end" is a reserved keyword) can u please help me.. - Altera_Forum
I have copied the code in Quartus II and I am unable to reproduce those messages after a file analyze command. Try to review all your code and search for missing brackets or semicolons. Sorry but I haven't got any other suggestions since I am not able to reproduce the messages.
