chess clock coding using quartus II

The chess clock is a simple finite state machine (FSM) which you can firstly design as a state diagram just figuring out the various states in which the machine will work in dependance of the external inputs and of the current states.

After having completed the FSM schematization you will have to translate everything into HDL code (maybe Verilog or VHDL) and put it into a new Quartus II project.

Do you need specific help for the chess clock project or also a comprehensive tutorial on Quartus II environment and FSM design?