changes in the constant parameter affecting the logic

Changing value of x changes the logic means obviously x is being used in the logic to affect the result. So obviously you cannot randomly change value of x without first understand what it does. You need to see where x to used and how it's used and then things will become clear.

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Making some unwanted changes which is not a logical change affecting the complete logic...

For eg.. VHDL syntax

constant x : std_logic_vector(15 downto 0):=x"af11";

this value is used in my logic while transmitting a ethernet packet. if i am changing the constant parameter to any other value my logic is not working.

what could be the issue?

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