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Altera_Forum's avatar
Altera_Forum
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14 years ago

changes in the constant parameter affecting the logic

Making some unwanted changes which is not a logical change affecting the complete logic... For eg.. VHDL syntax constant x : std_logic_vector(15 downto 0):=x"af11"; this value is used in my l...
Altera_Forum's avatar
Altera_Forum
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14 years ago

A constant is meant to be there as constant for some purpose.

You tell us why do you want to change it and what does it do?

A constant is not variable(I believe) and is used instead of embedding numbers directly in code in various parts that makes it difficult to change for any future update or purpose.