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I work with the version 8.0
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I generated the sopc builder and it generated the files .vhd
EXCEPT the file "name_sopc.vhd" where name_sopc is the name of your system sopc. So I don't have the toplevel.
This change is not enough.
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Someone using QII 8.0 SP1 told me that he changed from Verilog to VHDL for simulation by editing the hdlLanguage parameter.
As far as I know there is no officially supported way to change the SOPC Builder system language after the system is first created. Changing the language by modifying the hdlLanguage parameter in the .sopc file is a use-at-your-own-risk method. If it worked for the simulation file for the person I know though, I would expect it to work for all the HDL files generated by SOPC Builder for synthesis.
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I've not found a way of doing this through the GUI but I'm still using 7.2SP3 - later versions may have implemented this properly.
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The tool supports making this choice only when the SOPC Builder system is first created. That's not a bug. It's similar to having to choose the MegaWizard variation file language up front when you first configure a megafunction with the MegaWizard.
It would be nice if the tool were enhanced to allow this though. You could file a service request to ask for this. If enough people ask for it, it might be done.
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