Change bus width with a FIFO

Assuming you're writing a 64-bit value to the FIFO on every clock edge, then 'rdempty' is only going to be active for a single clock cycle when you first power up. Once you've written data to the FIFO it will go inactive, thus making your 'data valid' active permanently from then on.

Unless, your FIFO buffer size is very small. I can see a case whereby if you're only storing one 64-bit value before trying to read it then 'rdempty' could well go active again preventing any data from being read. I accept you've put a clock cycle delay between them but my suspicion is that may not be sufficient.

How big did you make your FIFO? Assuming the absolute delay through the FIFO is not of great importance, I suggest you try making it relatively big (anything over a depth of 4 should do) and delaying your 'rdreq' by more clock cycles. Ensure that you are writing 'a good number' of 64-bit values to the FIFO before you attempt to read from it.

For example: assuming a FIFO depth of 8, ensure you write at least 3 values in before you attempt to read from it. That way you're guaranteeing 'rdempty' never goes active (following the initial data being written).

Having said all that - I have to agree with Mux. I would be implementing this without the use of a MegaWizard FIFO and doing it in discrete flip-flops. A small array (2 or 4 deep) of 64-bit wide storage, written to using a write pointer on the slower domain. Read the data out using a read pointer having first latched the write pointer across to the faster domain. This will allow you to ensure the read pointer remains 180 degrees out of phase to the write pointer, thus never reading data too early or too late.

Regards,

Alex