Change Bar's size in PCIe Simulation

rsefton

Thank for reply!!

Yes, I've just got one BAR ..(BAR0)

I send you a image of my Qsys wired.

https://www.alteraforum.com/forum/attachment.php?attachmentid=13604

Inside, I've conected BAR0 to "avalon mm master translator" ( specifically in his port avalon_anti_master_) and I've conected master port of "avalon mm master translator" to tx port of my PCie avalon MM.... (please watch my image).

Friend, I've got another question for you

When you issue a TLP to PCIe wired or link (outside of interface) , Do you use Tx port of PCIe avalon MM (I refer, if you go to all interface signal of Tx such as TxsWrite, TxsRead, and so on....and you directly setup it) ???

or Do you use "Avalon MM Master Translator" to send data to Tx and then Tx alone issue PCIe TLP to outside of interface??

Thank for your helping!!