Change Bar's size in PCIe Simulation

If you read the user's guide for the PCIe Avalon-MM core it tells you that the BAR size is not configurable. The BAR has to be connected to something and Qsys figures out the BAR size from that. Seems a weird way to handle it but that's the way they did it, at least for Arria 10. In my case I just wanted to export the BARs from Qsys into my logic, but if you do that the BAR size defaults to 0. You have to put some kind of Qsys Avalon-MM bridge between the BAR and the outside world. I'm using the Avalon MM Master Translator. I set the address width in the Master Translator configuration and Qsys figures out the BAR size from that. This has worked fine for me so far.