Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Chaining DMA Scatter-Gather mode problems (SG-DMA)

Hey guys,

I got some problems in the Chaining DMA (CDMA) SG-DMA mode.

Based on the source code of the Altera PCI-E DEMO program, I am using WinDriver to develop the application. When transferring data more than 976 bytes, there are 2 pages in the CDMA descriptor table. Now, here come the problems.

Q1. The data length of the 1st page is always 82 DWords when generating the SOF with Quartus 10.0. and 62 DWords when generating the SOF with older version.

Is there anything to do with the Quartus version?

Q2. Why is it always 976 byes?

Is there any limitation in declaring a data buffer?

How does the WinDriver divide the buffer into pages?

The application sends data from PC to FPGA board, and holds a data buffer for receiving data from FPGA board to PC. Since the data transferring takes 2 pages, I check the data buffer part 1 and the part 2.

Comparing with the reference data, I find there is something lost in data buffer part 1 - the 1st 4 DWords are not transferred. And the 1st 4 DWords of part 2 overlap with the last 4 DWords of part 1.

Q3. How to avoid losing the 1st 4 DWords? How to avoid the overlapping thing?

Really need you guys help :(

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Did You debug the design by separating descriptor and data memories? E.g. descriptor to on-chip ram, which has enabled memory content editor?

    Also, do You flush the cache?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    1. i use func of "WDC_DMASGBufLock"(jungo-driver api) to decided descriptor parameters(descriptor numbers & data physical addr), but i can't known how this func does?

    2.which has enabled memory content editor? what does it mean?

    3.i use "WDC_DMASyncCpu"(jungo-driver api) to flush the cpu catches

    could you give me more information or suggestions?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I would debug in FPGA using signaltap in addition to jungo driver api. Edit the SOPC system, check where SGDMA descriptors are written and if they're in on-chip memory, go to properties and enable memory content reading/writing.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    In the process of chaining dma, the smallest data dma_read & dma_write support in a TLP-unit is 4(DW). but actually, we find the data-playload of each TLP is not multiple of the 4(dw) sometimes, it will make mismatch of data in dma read then write .

    Ask: What shouled I do to make sure the data-length is multiple of 4 in DT(Descriptor -table), and also with the data-length of each TLP?