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Altera_Forum's avatar
Altera_Forum
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17 years ago

Capture the falling edge of signals in VHDL

Hi, Please bear me with a newbie's question: I want to capture a PWM signal's falling edge. But, I can not use "falling_edge" as the PWM signal is not a clock signal. Can any exper...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Register your PWM signal whose falling edge you want to detect and then AND the registered signal with the NOT of non-registered one.

eg.

pwm

pwm_reg

pwm_reg <= pwm; (always at clock)

falling_edge <= ~pwm & pwm_reg; (assign statement)

sorry i don't know vhdl that's why i have written like this. Hope you understand what i am trying to say.

-AmitGarg