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Altera_Forum
Honored Contributor
Honored ContributorCapture the falling edge of signals in VHDL
Hi, Please bear me with a newbie's question: I want to capture a PWM signal's falling edge. But, I can not use "falling_edge" as the PWM signal is not a clock signal. Can any exper...
Altera_ForumHonored Contributor
Honored Contributorkbs972-
thanks for your tips. I used the way proposed by mmtsuchi (http://www.alteraforum.com/forum/member.php?u=1585). It works basically but I met with some other problems http://www.alteraforum.com/forum/showthread.php?t=4848 My PWM signal is asynchronous to my clock and I first did some "calibration' to the PWM signal before further process the PWM signal such as cutting in some deadtime etc...
