Capture the falling edge of signals in VHDL

kbs972-

thanks for your tips. I used the way proposed by mmtsuchi (http://www.alteraforum.com/forum/member.php?u=1585). It works basically but I met with some other problems http://www.alteraforum.com/forum/showthread.php?t=4848

My PWM signal is asynchronous to my clock and I first did some "calibration' to the PWM signal before further process the PWM signal such as cutting in some deadtime etc...