Capture the falling edge of signals in VHDL

Random comment, but i think it is cool that 3 people both replied with something that will synthesize to close to the same code but look pretty different.

Pertinent comment: If the PWM signal is asynchronous to the clock you are sampling it with, you may want to clock the PWM signal through a few ff's first so you don't have any metastability issues. If it is on the same clock domain as the sample clock then you don't need to worry about it obviously.