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Altera_Forum's avatar
Altera_Forum
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17 years ago

Capture the falling edge of signals in VHDL

Hi, Please bear me with a newbie's question: I want to capture a PWM signal's falling edge. But, I can not use "falling_edge" as the PWM signal is not a clock signal. Can any exper...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Looks like a few other people jumped on this one, as well. I think one of these should work :)