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Altera_Forum
Honored Contributor
Honored ContributorCapture the falling edge of signals in VHDL
Hi, Please bear me with a newbie's question: I want to capture a PWM signal's falling edge. But, I can not use "falling_edge" as the PWM signal is not a clock signal. Can any exper...
Altera_ForumHonored Contributor
Honored ContributorLooks like a few other people jumped on this one, as well. I think one of these should work :)
