Capture the falling edge of signals in VHDL

If you're strictly looking for the falling edge of the signal, you can use a clock to buffer the previous sample of the signal, and then look for a binary "10".

Something like this should work. I'd be curious if anyone has a better way to do it :)

if nreset = '0' then

sig_buf <= '0';

elsif rising_edge(clk) then

sig_buf <= sig_in; -- buffer the input signal on each clock

if ((sig_buf = '1') and (sig_in = '0')) then --see if falling edge exists

<this is your condition>

else

<keep waiting>

end if;

end if;