Capture the falling edge of signals in VHDL

hi,

maybe you should sample your pwm signal with a clk. every clk's rising edge check the pwm signal state (in the process you need a last state variable, to know the pwm's last state). if there is a change - there was a edge in the pwm signal.

some thing like that...

process(clk)

variable last_state: std_logic := '0';

begin

if clk='1' and clk'event then

--if last_state = '0' and pwm_signal = '1' then --rising edge

if last_state = '1' and pwm_signal = '0' then --falling edge

-- pwm edge

end if;

last_state := pwm_signal;

end if;

end process;

your clk must be fast enough to detect edges ;)

hope it helps!

have a nice day

joerg