Capture the falling edge of signals in VHDL

process(reset_n,clk)
      variable detect : std_ulogic_vector (1 downto 0);
   begin
      if reset_n ='0' then
         detect := "00";
      elsif rising_edge(clk) then
         detect(1) := detect(0); -- record last value of sync in detect(1)
         detect(0) := sync ; --record current sync in detect(0)
         
         if detect = "01" then -- rising_edge
         elsif detect = "10" then --falling_edge
         end if;
      end if;
end process;