Can't resolve multiple constant drivers for net "next_state"

This is slight modification of your code, it works, and is a different approach to writing state machines in verilog:

module Verilog_Traffic(R, G, Y, clock, reset);

output R, Y, G; // Red, Yellow, Green Signal lines

input clock, reset;

reg R, Y, G;

//state machine parameters

reg [1:0] present_state, next_state;

parameter Green = 2'b00,

Yellow = 2'b01,

Red = 2'b10,

Reset_State = 2'b11;

always @ (posedge clock)

begin

if(reset)

present_state = Reset_State;

else if (~reset)

present_state = next_state;

end

always @ (present_state)

case (present_state)

Green:

begin

G = 1'b1;

R = 1'b0;

next_state = Yellow;

end

Yellow:

begin

Y = 1'b1;

G = 1'b0;

next_state = Red;

end

Red:

begin

R = 1'b1;

Y = 1'b0;

next_state = Green;

end

Reset_State:

begin

R = 1'b0;

Y = 1'b0;

G = 1'b0;

next_state = Red;

end

endcase

endmodule