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Altera_Forum's avatar
Altera_Forum
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15 years ago

Can't fit design in device

Hi All!

I'm using EPM240T100 that has 240 logic elements. While compliling simple program i get an error:

Can't fit design in device.

For example this simple piece of code adds 42 logic elements:


process(CLK,REAR_ON)
begin
  if(rising_edge(CLK)) then
     if(REAR_ON <= '1') then
       reardim <= NAVDIM;
    else
       reardim <= "00000";
    end if;  
  end if; 
end process;

before 217/240(90%)

after 259/240(108%)

What do i miss?

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    the code is full of mistakes... Generics, if conditions, etc... When You write REAR_ON <= '1' it doesn't check the condition, it does the assignment.

  • Altera_Forum's avatar
    Altera_Forum
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    The next compatible device is the EPM570T100.

    There is some room to gain some LE's. You are using 4 separate PWM's. THe compiler reduces this to 3 as the REAR and the NAV have the same dimming settings (for the moment), this explains the 'sudden' 47 difference. If you consolidate the PWMs into one tick counter and 4 (better 'n') comparison operators you can save up to (n - 1) * 16 LEs. In theory Quartus II could do that on its own ... I think if you re-write the PWM-module so that the PWM_ENA is used inside the 'if rising_edge( Clk ) - end if;' construct it will share the ticks counter. A quick try confirms this, but I didn't check the functionality.
  • Altera_Forum's avatar
    Altera_Forum
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    Thanks a lot everyone! I'll try all your suggestions.

    Replacing "<= "with "=" in if statements gave significant improvement.
  • Altera_Forum's avatar
    Altera_Forum
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    Way off : Your intend to use clocked process but you wrote process(clk, other_signal) wich is not what you want (if we look inside the process). You may write

    
    process(clk) -- no other signal in sensibility list
    begin
       if rising_edge(clk)
          -- synchronous sequential statement here
       end if;
    end process;