Can't fit design in device

I think the compare conditional ( if(REAR_ON <= '1') ) is using resources.

REAR_ON : in std_logic; --on/off pin

Hi john

This simple change to if(REAR_ON = '1') increased logic elements,

Is it possible to find a chip with more logic elements and the same package and pinout?

I don't know EPM240T100 device, so I don't know how many LE are required.

process(CLK,REAR_ON)
begin
  if(rising_edge(CLK)) then
     if(REAR_ON <= '1') then
       reardim <= NAVDIM;
    else
       reardim <= "00000";
    end if;  
  end if; 
end process;

This is the complete design:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.all;
entity main_control is
port
(
  --Inputs
  CLK : in std_logic; --On-board system clock --
  FLDDIM : in std_logic_vector(4 downto 0); --flood dimming level select
  FORMDIM : in std_logic_vector(4 downto 0); --formation dimming level select
  NAVDIM : in std_logic_vector(4 downto 0); --navigation dimming level select
  CODES : in std_logic_vector(4 downto 0); --anticollision codes
  MODES : in std_logic_vector(3 downto 0); --lights modes
  REAR_ON : in std_logic; --1 - nav rear white on, 0 - off
  --Outputs
  FLOOD : out std_logic; --flood
  NAV : out std_logic; --navigation = position
  ANTICOL : out std_logic; --anticol
  REAR : out std_logic; --rear navigation
  FORM : out std_logic --formation
);
end main_control;
 
architecture arch_main_control of main_control is
  component pwm_module is
  generic
  (
   PERIOD : integer
  );
  port
  (
    -- Input ports
    PWM_CLK : in std_logic;
    PWM_ENA : in std_logic;
    DIM_SEL : in std_logic_vector(4 downto 0);
    -- Output ports
    PWM_OUT : out std_logic
  );
  end component;
 
  signal modes_buf : std_logic_vector(3 downto 0);
  --signal code : std_logic_vector(4 downto 0); --anticollision codes
  signal reardim :std_logic_vector(4 downto 0);
 
  signal flood_ena, form_ena, nav_ena, rear_ena, anticol_ena: std_logic;
 
begin
  process(CLK,MODES)
  begin
    if(rising_edge(CLK)) then
      case MODES is
        when "0000" => --covert - ir mode
          flood_ena <= '1';
          form_ena <='1';
          nav_ena <= '1';
          rear_ena <= '1';
          anticol_ena <= '1';
        when "0001" => --both
          --mode <= 1;
        when "0011" => --friendly
          flood_ena <= '1';
          form_ena <='1';
          nav_ena <= '1';
          rear_ena <= '1';
          anticol_ena <= '0';
        when "0111" => --off
          flood_ena <= '0';
          form_ena <='0';
          nav_ena <= '0';
          rear_ena <= '0';
          anticol_ena <= '0';
          --mode <= 3;
        when "1111" => --normal
          flood_ena <= '1';
          form_ena <='1';
          nav_ena <= '1';
          rear_ena <= '1';
          anticol_ena <= '1';
        when others =>
         --mode <= 3;
      end case;
    end if;
  end process;
 
  process(CLK,REAR_ON)
  begin
    if(rising_edge(CLK)) then
      if(REAR_ON <= '1') then
        reardim <= NAVDIM;
      else
       reardim <= "00000";
      end if;
    end if;
  end process;
 
  PWM1: pwm_module
  generic map(PERIOD => 20000)
  port map
  (
  PWM_CLK=>CLK ,PWM_ENA=>flood_ena, DIM_SEL => FLDDIM, PWM_OUT=>FLOOD
  );
 
  PWM2: pwm_module
  generic map(PERIOD => 20000)
  port map
  (
  PWM_CLK=>CLK ,PWM_ENA=>form_ena, DIM_SEL => FORMDIM, PWM_OUT=>FORM
  );
 
  PWM3: pwm_module
  generic map(PERIOD => 20000)
  port map
  (
  PWM_CLK=>CLK ,PWM_ENA=>nav_ena, DIM_SEL => NAVDIM, PWM_OUT=>NAV --navigation red-left,green-right
  );
 
  PWM4: pwm_module
  generic map(PERIOD => 20000)
  port map
  (
  PWM_CLK=>CLK ,PWM_ENA=>rear_ena, DIM_SEL => reardim, PWM_OUT=>REAR --navigation rear-white
  );
 
end arch_main_control;
 
pwm module:
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.all;
 
entity pwm_module is
generic
(
  PERIOD : integer
);
  port
(
  -- Input ports
  PWM_CLK : in std_logic;
  PWM_ENA : in std_logic;
  --PERIOD : in std_logic_vector(15 downto 0);
  DIM_SEL : in std_logic_vector(4 downto 0);
  -- Output ports
  PWM_OUT : out std_logic
);
end pwm_module;
 
architecture arch_pwm_module of pwm_module is
  signal ticks : std_logic_vector(15 downto 0);
  signal duty : std_logic_vector(15 downto 0);
begin
 
  process(PWM_CLK,PWM_ENA,duty)
  begin
    if(PWM_ENA <= '1') then -- pwm enabled
      if(duty <= PERIOD) then --handle extrim cases - on
        PWM_OUT <= '1';
      elsif(duty <= "0000000000000000") then -- handle extrim cases - off
        PWM_OUT <= '0';
      else
        if(rising_edge(PWM_CLK)) then
          if(ticks <= PERIOD) then --when overflow - reset
            ticks <= (others => '0');
            PWM_OUT <= '1';
          elsif(ticks <= duty) then --when duty - toggle
            PWM_OUT <= '0';
            ticks <= ticks + 1;
          else
            ticks <= ticks + 1;
          end if;
        end if;
      end if;
 
    else
      PWM_OUT <= '0';
    end if;
  end process;
 
  process(PWM_CLK,DIM_SEL)
  begin
    if(rising_edge(PWM_CLK)) then
      case DIM_SEL is
        when "00000" =>
          duty <= "0000000000000000"; --0
        when "00001" =>
          duty <= "0001001110001000"; --5000
        when "00011" =>
          duty <= "0000000000000000"; --10000
        when "00111" =>
          duty <= "0000000000000000"; --14000
        when "01111" =>
          duty <= "0000000000000000"; --17000
        when "11111" =>
          duty <= "0100111000100000"; --20000
        when others =>
      end case;
    end if;
  end process;
 
end arch_pwm_module;

rear_ena <= '1'; 
with          
rear_ena <=  REAR_DIM;
and
  PWM4: pwm_module
  generic map(PERIOD => 20000)
  port map
  (
  PWM_CLK=>CLK ,PWM_ENA=>rear_ena, DIM_SEL => NAVDIM, PWM_OUT=>REAR --navigation rear-white
  );

Thanks a lot for your effort. Even with optimization i still have some modules to implement. What chip could rplace this one , considering the same pinout?