Can't close timing on one clock domain

One big issue I see is that your report indicates that a burst adapter is getting added into your Qsys system design which adds a large amount of combinatorial delay into the interconnect. There's a number of possible reasons for this.

Data path (master / slave) width mismatch

Either master or slave can use a burst and have a burst count field on Avalon interface

When master is bursting to a slave and there’s a data width mismatch

Matching data path width but different burst counts

Burst count fields in the master and slave may be different widths

Master with narrower burst count width than slave: not usually a problem

Slave has narrower burst count width than master: adapter needed to split burst into smaller bursts; should be resolved if possible

Burst type not supported by slave

Example: AXI master bursting to an Avalon slave

Solutions: match burst widths if possible or use a pipeline bridge component, matching the burst widths on either side of the bridge. So if you have a burst width of 8 from a master and slaves only support a burst of 1, add a pipeline bridge between the master and slaves with a width of 8 on its slave side and a width of 1 on its master side.

You can also add pipeline stages inside the interconnect on the Interconnect Requirements window in Qsys or manually in the Show System with Qsys Interconnect option from the Qsys System menu.