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Altera_Forum's avatar
Altera_Forum
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16 years ago

Can't achieve minimum setp and hold time error?? :((

The scenario is that I have a (1) grey code counter connected to a (2)combinational block that goes into a (3)parallel In parallel out register from there. There are 2 inputs from the Grey counte...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It's a hold violation, so I would say almost with certainty you have a gated clock to keyStoreMem:inst2|FF*. You can do the List Paths to determine this too. Describing the circuit doesn't help much.

The only thing that's "strange" is that all your slacks are the same. In generally they're going to vary to each destination(even if they're all failing), but I'm not sure why.

Anyway, have you done the List Paths? What have you found from this?