Honored Contributor
Honored Contributorsee I have a block with Parallel in parallel Out D flip flops. The CLK to them has been inverted by using a NOT gate and Also I have use a D flip flop to create a Clock enable thing instead of an AND gate having a clock enable and CLK signal input.
Then I have a Grey Counter that still has the AND gate with the Clock enable and CLK inputs. I replaced that with a D flip flop with the Clock enable going into D and the CLK going into its clock input in order to replace the AND gate but then nothing works. What should I do. This is the first time I am working on Quartu. Is there any advice that you may give me then?
