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Altera_Forum
Honored Contributor
Honored ContributorCannot write using FPGA2HPS and FPGA2SDRAM AXI ports
Hi everyone! I'm currently in the process of transferring some IP cores with AXI interfaces from the Zynq to the Cyclone V SoC. However, while reading from the DDR memory using an AXI master po...
Altera_ForumHonored Contributor
Honored ContributorJust in case someone has the same problem: I found out that in fact the AWREADY signal from the FPGA2SDRAM port to the AXI interconnect was working just fine. However, the AWREADY signal from the AXI interconnect to my IP core was stuck at 0.
In the end I "solved" my problem by re-importing my IP core into QSYS and marking my AXI master port as an AXI3 port. Originally, I had marked it as an AXI4 port although I only used the AXI3 functionality. Apparently, something went wrong with the translation from AXI3 to AXI4.
