Cannot assign clock signal to XCVR bank pin - Arria 10

Hello FvM,

I used the "Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP" for generating clock signal, the data part should not be a problem to generate output serialized signal as you mentionned. However it doesn't appear very clear to me what clock(s) I should assign to this IP. Here are some details :

I have to supply 2 clock inputs to the transceiver , and - I suppose - to its CGB, which are :

- tx_serial_clk0

- tx_coreclkin

I saw from the IP datasheet that coreclkin frequency should be ( Datarate / (parallel_data) ) which is 1GBPS / 8bits = 125 MHz.

It is also mentionned in the picture above that the "TX PLL IP" must provide a clock frequency of 500 MHz related to internal clock division factor. I couldn't find more detail in datasheet to explain if this clock is the serial or core one, which is a bit confusing.

Anyway, the way I assigned clocks, and corresponding to Arria 10 pins, is the following :

- reference_clk from FPGA core (CLK_50_B2H - 50 MHz) -> IOPLL (125 MHz) -> tx_coreclkin

- reference_clk_from_FPGA core (CLK_50_B3H - 50 MHz) -> fPLL (500 MHz) -> tx_serial_clk0

The compilation fails during fitter. I also used dedicated transceiver reference clock CLKUSR_100 for the fPLL instead of the 50 MHz user clock, and I have in any case same error which is :

Input port "REFCLK" of "CMU_FPLL_REFCLK_SELECT" cannot connect to PLD port "O" of "IO_INPUT_BUFFER" for node "CLKUSR_100~input".

What is strange is that it shows here an error related to fPLL reference clock, while when I remove the Transceiver IP, the compilation is successful. So I guess it is rather related to Transceiver reference clocking rather than fPLL reference clocking ?

I would be grateful if you could enlighten me on this !

Thanks