Can not write or read in SDR SDRAM

I can confirm, that the WP SDRAM code is basically working. Depending on the FPGA family, constraints may be necessary to enforce e.g. the usage of fast OE registers. But because you are only showing a sub-entety of your code, nobody can check if you interfaced the SDR code correctly. Also, you apparently had to apply some changes to the originally 16-Bit wide code. There are many details, that may have gone wrong adapting the code.

I didn't check, if you possibly missed something essential in the RAM handling, because I prefer to see the whole thing, first.

I don't know, if I'll have the time to check the code in detail. But also for others, that can possibly help: Please assemble a minimal test project, including the SDR code and all pin assignments (I guess, you're using an existing Dev. Kit) in a *.qar project archive.

P.S.: In the meantime, you should learn how to use SignalTap II to display the RAM signals. Start with the RAM initialisation, then write, read. Check if all RAM signals are as they should be expected according to the Micron RAM datasheet respectively the controller documentation.