Contributor
ContributorWhile I have been designing with FPGA's for 20 years, I have always adhered to the rule of no more than 50% FPGA device utilization when releasing a product to the field. Most large companies have a rule around this number.
However, this particular design has been tested extensively and I questioned the company as to whether there would be any future modifications. They answer is "NO" so the responsibility is on them for any issues that may arise with not having enough space.
However, in the process of doing the project, Quartus is able to synthesize the design to 96% full with ease, and this was a great surprise. The whole design synthesizes in less than 2 minutes. This prompts me to ask the question to Intel and the community at large about whether its even possible to fill the chip 100%.
This is an outlier case of fill percentage, so this is definitely not the norm, but still very worthwhile to understand the possibilities.
