Forum Discussion
mbran15
New Contributor
New Contributorcan i use quick sorting in HDL(Verilog or VHDL)?
module sort_ex ( clk, rst, out);
parameter SIZE = 10;
input clk, rst;
output reg [6:0]out;
reg set_end, loop_check, loop_on1, loop_on2, loop_on3;
reg [8:0] arr [SIZE-1:0];
reg [8:0] temp;
reg ...
ak6dn
Regular Contributor
Regular ContributorWell, even beyond the blocking/non-blocking assignment issue, using constructs like 'for' and 'while' are going to produce non-synthesizable code.
Ok for behavioral simulation, not so much for synthesis.
