Forum Discussion
Altera_Forum
Honored Contributor
7 years agoIts probably because you have fout_data and data being the same signal.
INOUTs should only connect directly the to top level, you appear to have it connected to part of your design and the pin? Another point - you have DATA connected to (others => '0') when BE_out_en is not '0' or '1'. If this is a trap for simulation faults, it is much safer if you connect it to (others => 'X').