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Altera_Forum
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8 years ago

Can I produce 4 MHz from a 10 MHz input?

Hi All, I have a Cyclone IV board. Can I produce 4 MHz from a 10 MHz input? I am totally new to this field. I can produce 4 MHz using the 50 MHz on-board clock using PLL. But it seems GPIO ca...
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Altera_Forum
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8 years ago

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I guess, the Cyclone III/IV constraint is enforced by the design software on purpose. Dropping it for Cyclone V might be just a bug.

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It's not a software bug at all. In fact it is due to a major difference between the design of the clock routing networks in the CV devices compared with their older family.

If you compare page 4-11 of cyclone v datasheet (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf) with page 5-11 of the cyclone iv datasheet (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51005.pdf) you can see there is a distinct difference in the clock routing networks of the two devices.

In the Cyclone IV devices, PLLs are fed directly from the CLK[N] dedicated inputs, whilst the GCLK network is fed through a separate mux. As such it is not possible to route back from the global clocks into the PLLs.

Comparatively in the Cyclone V devices, PLLs are fed from multiplexers which can select between the dedicated CLK[N] inputs and the GCLK network. As such any global clock (or periphery and regional clock) can feed directly to the PLL reference clock inputs.