--- Quote Start ---
It's true that PLLs have dedicated clock inputs, these give the best performance, but I was able to assign a GPIO as a PLL input on my Cyclone V (not Cyclone IV) device using the global_clock buffer IP. Maybe this is feasible on the Cyclone IV as well?
--- Quote End ---
Interestingly Cyclone V device handbooks says it's no feasible:
--- Quote Start ---
Internally-generated GCLKs, RCLKs, or PCLKs cannot drive the Cyclone V PLLs. The input clock to the PLL has to come from dedicated clock input pins, PLL-fed GCLKs, or PLL-fed RCLKs.
--- Quote End ---
I guess, the Cyclone III/IV constraint is enforced by the design software on purpose. Dropping it for Cyclone V might be just a bug.
Honored Contributor
