Forum Discussion
Altera_Forum
Honored Contributor
8 years agoSee the second page of this PDF: https://www.mikrocontroller.net/attachment/177197/xl33_30.pdf
That's a divide by 2.5 digital circuit which could be implemented in an FPGA. 10MHz / 2.5 = 4MHz. It's not going to be a clean clock, there will be quite a lot of jitter, and it is not 50% duty cycle (gives 40% duty). It could be usable for many designs so long as you don't need sub-nanosecond accuracy.