Can i deserialize LVDS using DCFIFO ?

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Technically, isn't changing 1 bit to 16 bits possible?

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Only if the underlying dual-ported RAM supports writes at 16-bit and reads at 1-bit. Even if it doesn't, you can easily write a state machine to read in 16 x 1-bit values, and then write it to one port of a RAM at 16-bits. The reader on the other side would also read 16-bits. From the top-level, this component would look like a 1-bit to 16-bit deserializer.

This however only works if the clock rate of your 1-bit data can be dealt with by the FPGA. The whole point on the hard-IP LVDS SERDES is that they operate at much higher frequency than the fabric logic elements.

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I've tried altlvds_rx, it could only go up to 10 bits.

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So, that is all they need to do. Take for example a 1Gbps data stream (which is near the fastest the LVDS SERDES can run). If you operate the SERDES in 1:8 mode, then inside the FPGA, the parallel data is 1GHz/8 = 125MHz. If you want 16-bits or 32-bits inside the FPGA, just do that demultiplexing using logic elements.

Cheers,

Dave