Can DMA do NOT use a same clock with PCIe IP when using Cyclone IV GX?

> And for the first question,

> for PCIe transmit,the sender has to use a same clock with PCIe.

sorry I don't get it

> ARM knows that it is done.

> BUT,in this case,How does the PCIe IP know the transfer is done?

>The IRQ is just sent through PCIe IRQ channel.The PCIe doesn't know the meaning of IRQ.

of cause not.

PCIe is a bus protcol.

how shoud IP-core know the dma done?

bus IP-core just transfer information between busmasters and slaves.

interrupt is just information of its status.

> And accroding to the PCIe protocal,there are data length in TLP,how does PCIe IP knows the payload length?

I don't know which IP-core you use.

but there must have the setting for payload size.

payloadsize is fixed before you compile FPGA.

and knowing payload size is not your job.( setting it is yours )

are you creating PCIe-IP core on you own?

if so, I'm sorry forget about all my advice.

do you still have question?