Forum Discussion
Altera_Forum
Honored Contributor
13 years agouse dual clock FIFO between DMA-IP annd PCIe-IP.
the FIFO solve timing problem unless receiver's data rate is slower than sender's. the other question. when PCIe-IP know the DMA is done? there should be interrupt signal. when interrupt becomes high, your BUS-Master ( ARM in this case ) knows it is done.