Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCan DCFIFO rdreq and wrreq signal be valid simultaneously?
The rdclk and wrclk in my design is nearly the same frequency but not the same phase. I enabled the full and empty protect. My question is can rdreq and wrreq signal be valid simultaneously?
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yes. But they should be valid with respect to their individual clock domain. Meaning don't assert wrreq with the read domain clock and vice-versa. Jake --- Quote End --- I have another question: can rdreq signal be always high? I met a problem that I set the rdreq signal to be '1' all the time, first the FIFO can work properly, after running for sometime it can not work successfully. I don't know if it is reason of rdreq signal. I simulated it with modelsim, it is OK.
