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Altera_Forum's avatar
Altera_Forum
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16 years ago

Can DCFIFO rdreq and wrreq signal be valid simultaneously?

The rdclk and wrclk in my design is nearly the same frequency but not the same phase. I enabled the full and empty protect. My question is can rdreq and wrreq signal be valid simultaneously?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Yes. But they should be valid with respect to their individual clock domain. Meaning don't assert wrreq with the read domain clock and vice-versa.

Jake

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I have another question: can rdreq signal be always high? I met a problem that I set the rdreq signal to be '1' all the time, first the FIFO can work properly, after running for sometime it can not work successfully. I don't know if it is reason of rdreq signal. I simulated it with modelsim, it is OK.