Altera_ForumHonored Contributor16 years agoCan DCFIFO rdreq and wrreq signal be valid simultaneously? The rdclk and wrclk in my design is nearly the same frequency but not the same phase. I enabled the full and empty protect. My question is can rdreq and wrreq signal be valid simultaneously?
Recent DiscussionsVcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0Arria 10: Remote Update Factory Fallback won't work & Watchdog does not triggerIBIS models GTS banks agilex 5EClarification on Arria 10 Design Security Featuresrsu_client failing to write to slot