Can conditional builds be performed in VHDL?

Oliver:

I'm not familiar with AHDL, but I suspect that the "PARAMETER" statement you refer to

is the same as VHDL's "generic". I've used that before, but for parameterizing between

two levels only. I suspect that there would need to be a precedence rule when passing

a parameter between multiple levels.

In the case of my recent experiment with generic/generate, I used that to cut down on

editing between simulation vs. system build versions. The previous engineer for this

project would comment out and uncomment portions of code each time. I modified

the lower level entity with a generic to default as a simulation version by generating

it's own signals normally passed in on input ports from the higher level entity. The

higher level entity that instantiates the lower overrides the lower level entities’

generic default by passing in a value to use the system build version of code.