Altera_Forum
Honored Contributor
16 years agoCan Altera's sync_FIFO or async_FIFO be dead?
Hi,
There is a sync_FIFO or async_FIFO in a design. If we write data into it when it's full or read data from it when it's empty, is there any chance that the FIFO will be dead? I mean, in this case, we could not write any data into it no matter it is full or not, or we could not read correct data from it any more. If the FIFO is turely dead, we could make it alive again except power-off-and-on? Can a positive pulse on asynchronous clear be useful? Do we have any means to avoid this phenomenon? Best Regards