Can a PLL be implemented in a CPLD

Hi,

There are two issues here, one related to actual design and the other related to vhdl

1) your fast clk is 10MHz, slow is 1Hz. So without doubt your ratio is very high. You need to look at edge of clk1Hz and compare it with clk10MHz only when both edges are expected to lock. i.e. if slow counter is 0~3 then fast counter will be 0~(2^26-1).

So only when reaching maximum counts you need to drive the relevant flipflops.(max count = 3 or 40 million-1)

Clearly the design will take 4 sec per test so you expect the lock to take few seconds, unless you have means of multiplying clk1Hz(FPGA PLL can do that).

2) The code:

you can reduce the ports to:

port(

clk1 : in STD_LOGIC;

clk2 : in STD_LOGIC;

cp_n : inout STD_LOGIC;

cp_p : inout STD_LOGIC;

locked : out STD_LOGIC

);

you declare the delay nodes internally and you must drive them then use them in the AND statement.

cp_n_d <= cp_n;

cp_p_d <= cp_p;

clr <= cp_n_d and cp_p_d;

your flipflop drive is ok except for count values. So is the detection logic;

Always check at the extremes of your counters(not my counters)

Good luck