Honored Contributor
Honored ContributorHi,
Not being a VHDL expert, does the following look accurate to you. use library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ----------------------------------------- entity PhaseDetector is port( clk1 : in STD_LOGIC; clk2 : in STD_LOGIC; cp_n_d : in STD_LOGIC;-- delayed?? cp_p_d : in STD_LOGIC;-- delayed?? cp_n : inout STD_LOGIC; cp_p : inout STD_LOGIC; locked : out STD_LOGIC ); end PhaseDetector; architecture behav of PhaseDetector is signal clr : STD_LOGIC ; signal clk1_cnt: integer range 0 to 255; -- clk1 counter signal clk2_cnt: integer range 0 to 7; -- clk2 counter begin process -- counter on clk1 begin wait until clk1 = '1';-- clk1 is VCXO signal clk1_cnt <= clk1_cnt + 1; end process; process -- counter on clk2 begin wait until clk2 = '1'; -- clk2 is PPS signal clk2_cnt <= clk2_cnt + 1; end process; process (clk1,clr) -- clk1 flip-flop begin if (clr = '1') then cp_n <= '0'; elsif rising_edge (clk1) then if (clk1_cnt = 7) then -- adjustment value cp_n <= '1'; end if; end if; end process; process (clk2,clr) -- clk2 flip-flop begin if (clr = '1') then cp_p <= '0'; elsif rising_edge (clk2) then if (clk2_cnt = 3) then -- adjustment value cp_p <= '1'; end if; end if; end process; -- reset when both outputs are high clr <= cp_p and cp_n; -- PLL lock detector process begin if (clk2_cnt = 3) then if (clk1_cnt = 7) or (clk1_cnt = 0) then locked <= '1'; else locked <= '0'; end if; end if; end process ; end behav;
