Forum Discussion
Altera_Forum
Honored Contributor
17 years agoHi,
My design of the phase comparator is based on this basic idea: clk1 sets a flipflop to ‘1’ at its edge. clk2 sets another flipflop to ‘1’ at its edge both flipflops are then reset asynchronously by their ANDed output (after some delay). Thus the duration of each Q pulse will indicate the distance between edges of the two clks. In practice you don’t need to check each and every clk edge as this may be excessive leading to a swing effect, you can choose how often by using counters. These counters will also help detect the lock state.The value of counters is implementation dependant according to clk ratio and your low pass filter.. In my case the ratio was 2 and I used two counters: 0 ~ 7 on fast clk 0 ~ 3 on slow clk cp_p & cp_n are the Q outputs of flipflops and used for the charge pump. (Adjust it’s sense as required). cp_p_d & cp_n_d are the delayed version for reset(I used wiring to bidirectional IO and back) Rememebr to use fast io registers for Q outputs your clk ratio is too high and you may need to play around for best counting and filter cutoff The following code section may help ------------------------------------------------------------------------------------------------------------ process -- counter on clk1 begin wait until clk1 = ‘1’ clk1_cnt <= clk1_cnt + 1; end process; process -- counter on clk2 begin wait until clk2 = ‘1’ clk2_cnt <= clk2_cnt + 1; end process; process (clk1, clr) -- clk1 flip-flop begin if (clr = '1') then cp_n <= '0'; elsif rising_edge (clk1) then if (clk1_cnt = 7) then cp_n <= '1'; end if; end if; end process; process (clk2, clr) -- clk2 flip-flop begin if (clr = '1') then cp_p <= '0'; elsif rising_edge (clk2) then if (clk2_cnt = 3) then cp_p <= '1'; end if; end if; end process; -- reset when both outputs are high clr <= cp_p_d and cp_n_d; -- PLL lock detector process begin wait until clk1 = ‘1’; if (clk2_cnt = 3) then if (clk1_cnt = 7) or (clk1_cnt = 0) then locked <= '1'; else locked <= '0'; end if; end if; end process ; ----------------------------------- good luck