Can a PLL be implemented in a CPLD

Basically, you have to design the PLL according to your requirements. A CPLD can make the digital part of it. Because of the huge frequency ratio, I guess that a digital PLL, using a Sigma-Delta DAC to control the VCXO may be meaningful, particularly if your intending low phase noise.

It's mainly a matter of good system design, the type of utilized digital logic is of secondary importance to my opinion. And it's almost clear, that the PLL components present in most FPGA are of no use for this application.