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For a new desing I am planning to implement the Deserializer for CamerLink in the FPGA to replace the Deserializer chip. To protect the FPGA I/O's (ESD) I thought to place a "sacrificial" LVDS buffer between CameraLink connector and FPGA. But the "sacrificial" buffers need more space on the board and they are more expensive then the Deserializer.
Another option is to do it without the "sacrificial" buffer. What is your opinion about this? How well are the FPGA (Cyclone IV) I/O's protect against ESD damage. Is there any other way to protect the FPGA I/O's for damage?
Your opinion is highly appriciated.
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I have an issue with Cyclone IV directly driving a Cameralink video, it is extremely vulnerable, the failure rate is very high. My previous board was based on Cyclone II and it NEVER failed!
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