CAM the hard way or how to compare against thousands of bits?

You have basically correct RTL in both cases, but both will require 160K flops rather than 160K bits of SRAM. With SRAM inside an FPGA, you can read one value per cycle, so you can only compare the input to one value at a time. Only some of the largest FPGAs have more than 160K flops, I think that it's just the ones over $1K.

If your constraints allow you to use 5K clocks to read all of the SRAM entries, then you can easily fit this into an FPGA.

But if you need the compare results faster, then you will probably need to use an external CAM, or consider alternative approaches, such as binary trees.

You will find a few references to implementing CAM in FPGAs using SRAM, but those techniques usually only allow a small number of of compare values (it's hard to go much beyond ~100 entries).

\c