Calibration Clock in Stratix4GX Transcivers

I have a question, regarding the Calibration clock in Stratix4GX fpga. In my design, I have transceivers that use two seprate IPs. One set of Transceivers are using PCIe hard IP and the other set of Transceivers are using Hyper Transport3 PHY IP. The transeivers in both IP are located in such a way that they both need to share common CalClk. With HT3 Phy, due to power management support, the HT3 link goes down and comes back up every now and then. I am not sure if free running calibration clock is OK. Can they both use a free running 50MHz clock? Or is the requirement for CalClk diffferent for HT3 PHY IP? It will be great if you can help me answer this question.

Thanks.