As a general comment, it's much more easy to calcúlate it with a regular computer and some algebraic tool, that can handle large numbers.
In a Verilog (or another HDL), you have to select and implement a number scheme first. Verilog knows only signed and unsigned numbers, you have to introduce at least fractional signed numbers to achieve some accuracy. The advantage is, that Verilog numbers aren't a priori limited to a particular bit length, you can extend them to your needs (but within the resource restrictions of your hardware). The (-1)^n is a trivial problem, look sharp!