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Altera_Forum's avatar
Altera_Forum
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17 years ago

Bus mux issues

Hi all, Im new to this forum and fairly new to CPLDS, so please bear with me I have got by with schematic entry so far, and hope to keep doing so for the time being. Anyway my iss...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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Is it ok to tie the result and data togeather.

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I understand, that you have three external busses. Physically, three-state driver I/O cells are required for each of it. I'm not sure, how the compiler understands your logic. You can consult the Quartus netlist viewer to check. But I suggest to use 3 bidir I/O symbols with the external sides connected to the busses and wire the internal sides accordingly. This should clearly instruct the compiler what to do.