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TomCarpenter's avatar
TomCarpenter
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Bus LVDS on Arria 10 with Hardware Deserialiser

I'm trying to implement Bus-LVDS to communicate between a Cyclone IV and an Arria 10 device. For the Cyclone IV, I use the altlvds cores which are software serialisers, so no issue there. For the Ar...
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  • FvM's avatar
    FvM
    2 years ago
    SERDES IP doesn't seem to be able to connect other IO-standards than plain LVDS RX respectively TX. It's apparently necessary to write your own serdes logic in these cases. No problem as such if you don't run near device speed limits, but surely annoying.
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
SERDES IP doesn't seem to be able to connect other IO-standards than plain LVDS RX respectively TX. It's apparently necessary to write your own serdes logic in these cases. No problem as such if you don't run near device speed limits, but surely annoying.
TomCarpenter's avatar
TomCarpenter
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Yeah, I came to that conclusion.

Ended up rolling out my own soft-SERDES core using half-rate DDIO blocks. Managed to get it to meet timing at the 720Mbps we require. Couple that with some creative dynamic phase shifting of the PLL output clocks should hopefully allow dynamic phase alignment of the receive assuming it works once I get into hardware testing.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    Thanks for confirming. I would be happier if you had found a different solution.
    If I was an Intel support engineer, I'd try to find out the nature of limited SERDES connectivity. There are different possibilities:
    1. Restriction of hardware connectivity in silicon.
    2. Incomplete fitter implementation.
    3. Intentional constraint to keep certain specifications

    In the latter case there can be a "magic word" to override the constraint, to allow implementations that don't need maximum performance. BLVDS with its reduced speed could be such a case.