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Altera_Forum
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16 years ago

bursts with NIOS II and avalon-mm clock crossing bridge

My prob.: I have to store small data at high speed at the ddr ram(up to 20-160 bytes of data every 100µs). So maybe I need bursts. Just have to be fast when I write. The reading time doesnt bug me...
Altera_Forum's avatar
Altera_Forum
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16 years ago

You won't have bursts using the IOWR macro because it does a single write operation. To have bursts you need to either use a DMA engine that supports bursts, or have the CPU write to its data cache (using traditional pointers) and force it to dump the cache when finished.